1. Field of the Invention
The present invention relates generally to detecting boundaries or edges between different types of material which have been obstructed from view by an opaque layer, to thereby provide accuracy during such processes as semiconductor wafer alignment.
2. State of the Art
Edge detection is a well known technique used, for example, to align a layer of a component or device relative to another component or device. For example, when manufacturing semiconductor devices, a wafer upon which multiple semiconductor devices are to be formed must be aligned so that desired portions of the wafer can be subjected to photolithography and etching. Typically, a wafer, such as wafer 100 of FIG. 1A, is formed with multiple fields 102, 104, 106, 108 and so forth. For the sake of clarity, only four such fields have been shown in the FIG. 1A example, but those skilled in the art will appreciate that any number of such fields can be defined on the wafer 100. Each field typically includes an alignment mark 110, also referred to as a global alignment mark. This alignment mark is used during a photolithography process to accurately position a field with respect to a stepper that is used to expose portions of the field which are to be etched.
Referring to FIG. 1B, an alignment mark of an exemplary field 102 is illustrated in cross-section. The wafer is formed with a silicon substrate 112. At desired portions within the field 102, local oxidation silicon (i.e., LOCOS) regions, or oxide regions, 114 are formed (e.g., grown) to isolate the various devices formed in the field from one another. A polysilicon layer 116 is formed over the oxide regions and exposed portions of the silicon substrate 112. A photoresist layer 118 is then formed (e.g., coated) over the polysilicon layer 116.
When forming transistors in remaining portions of a field, the photoresist layer 118 is typically etched using a photolithography process. That is, portions of the photoresist layer 118 are masked, and unmasked portions are exposed to light (e.g., ultraviolet light). The exposed portions of the photoresist are etched using a conventional plasma etcher. Portions of the photoresist layer 118 which have been removed define a region within an exposed portion of the silicon substrate 112. For example, transistor sources and drains are established in this defined region. That is, the transistor is typically formed like the FIG. 1B alignment mark, except that a region (e.g., diffusion region 120) is defined as an area where source and drain regions are to be formed.
As those skilled in the art will appreciate, efforts to more densely form electronic components on wafers, such as wafer 100, have resulted in extremely small dimensions for the various components within each field. For example, recent generations of complementary metal-oxide silicon integrated circuits (CMOS) have gate regions with dimensions on the order of 0.25 microns (micrometers). As such, increased precision is required to accurately expose and etch portions of the photoresist layer 118. The alignment marks 110 must therefore be precisely identified so that the wafer can be properly positioned for photolithography.
In the past, conventional techniques for detecting changes in material characteristics of the alignment marks were deemed adequate for accurate wafer alignment. As shown in FIG. 1B , the alignment mark 110 is typically formed as a square silicon region within a surrounding oxide region. In FIG. 1C, a top view of the FIG. 1B alignment mark 110 is illustrated prior to formation of FIG. 1B polysilicon and photoresist layers. As shown therein, an exposed portion of the substrate 112 is represented as a square within a oxide region 114. Referring to FIG. 1B, oxide regions 114 are formed with a relatively steep contour 132 so that the boundaries, or edges 132 between the oxide regions 114 and the silicon substrate 114 can be accurately detected to align the field 102 for a photolithography process. Because the polysilicon layer 116 and the photoresist layer 118 were formed over the oxide regions 114 and the silicon substrate 112, they followed the surface contour of the wafer topography in existence prior to formation of the polysilicon layer 116.
To identify edges 132 of the substrate region which is labeled "x" in FIG. 1B, either dark field or bright field projection has typically been used, with a light source that will be reflected by the polysilicon layer. That is, an incident light beam 122 in the visible spectrum is directed perpendicular to the photoresist layer 118, so as to be transmitted through the photoresist for reflection by the polysilicon, the polysilicon being opaque with respect to the light source selected. Edges of the substrate region "x" are often detected using, for example, broad band or white light illumination (such as tungsten halogen sources), or monochromatic light using helium-neon (He-Ne) laser sources. The light sources are typically mounted internally to a stepper device used to perform the photolithography, and the alignment marks are detected using charge coupled device (CCD) cameras.
The visible light beam is selected for transmission through the photoresist layer 118 and for reflection as a reflected light beam 124 from the polysilicon layer 116. Because the surface contour of the polysilicon layer 116 is displaced in a downwards direction at boundaries between oxide region 114 and the silicon substrate 112, different angles of the reflected light beam 124 can be used to identify these boundaries.
For example, the visible light beam 122 would be reflected at an angle of a, at the boundary between the oxide region 114 shown to the left hand side of FIG. 1B and the silicon substrate 112. In contrast, a visible light beam 126 which is directed perpendicular to the photoresist layer 118 would be reflected along the path of the incident light; that is, the angle of a reflected light beam 128 with respect to the incident light beam 126 would be zero.
Although the foregoing process has been deemed satisfactory for detecting edges of an alignment mark 110 to position a wafer 100 for subsequent processing, recent developments in semiconductor processing have rendered this technique inadequate. The conventional detection of alignment marks 110 relies on the surface topography (such as the exposed upper surface of polysilicon layer 116) to vary in the vertical plane of FIG. 1B. However, problems exist when using this process with more recent integrated circuit fabrication technologies, such as 0.25 micron technology. With this more recently developed technology, local oxidation silicon isolation is often no longer used. Rather, shallow trench isolation (STI) is used, wherein chemical mechanical polishing (CMP) planarizes the topography of the alignment marks 110. Because the polysilicon layer is opaque to the conventional white light source and the HeNe source, and because the alignment marks have been planarized, boundaries between different materials used to form the alignment marks become undetectable with conventional edge detection processes. As such, the wafer 100 can no longer be aligned within the stepper.
Accordingly, it would be desirable to develop a process which does not rely on topographical surface variations to detect edges, and which is capable of detecting edges through one or more layers of material.